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| ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? 1 ? ? ? ? ? ? device highlights flexible programmable logic ? 0.18 m six layer metal cmos process ? 1.8/2.5/3.3 v drive capable i/o ? up to 1536 logic cells ? up to 4,002 flip-flops ? up to 310 i/o pins ? up to 335 user-available pins ? up to 320,460 maximum system gates embedded dual port sram ? up to twenty-four 2,304-bit dual port high performance sram blocks ? up to 55,296 ram bits ? ram/rom/fifo wizard for automatic configuration ? configurable and cascadable programmable i/o ? high performance i/o cell ? programmable slew rate control ? programmable i/o standards: lvttl, lvcmos, lvcmos18, pci, gtl+, sstl2, and sstl3 eight independent i/o banks three register configurations: input, output, and output enable advanced clock network ? nine global clock networks: one dedicated eight programmable ? 20 quad-net networks?five per quadrant ? 16 i/o controls?two per i/o bank ? four phase locked loops embedded computational units ecus provide integrated multiply, add, and accumulate functions. security features the quicklogic products come with secure vialink ? technology that protects intellectual property from design theft and reverse engineering. no external configuration memory needed; instant-on at power-up. figure 1: eclipse-e block diagram embedded ram blocks pll pll fabric embeded computational units embedded ram blocks pll pll fpga combining performance , density, and embedded ram eclipse-e family data sheet
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 2 quickworks design software the quickworks ? package provides the most complete esp and fpga software solution from design entry to logic synthesis, to place and route, to power calcul ation, and simulation. the pa ckage provides a solution for designers who use third-party tools from cadence, mentor, orcad, synopsys, viewlogic, and other third- party tools for design entry, synthesis, or simulation. programmable logic architectural overview the eclipse-e logic cell structure is presented in figure 2 . this architectural feature addresses today's register- intensive designs. table 1: eclipse-e product family members ql6250e ql6325e max gates 248,160 320,640 logic array 40 x 24 48 x 32 logic cells 960 1,536 max flip-flops 2,670 4,002 max i/o 250 310 ram modules 20 24 ram bits 46,100 55,300 plls 4 4 ecus 10 12 packages pqfp (0.5 mm) 208 208 lfbga (0.8 mm) 280 280 pbga (1.0 mm) 484 484 table 2: performance standards function description slowest speed grade fastest speed grade multiplexer 16:1 2.8 ns 2.4 ns parity tree 24 3.4 ns 2.9 ns 36 4.6 ns 3.9 ns counter 16 bit 275 mhz 328 mhz 32 bit 250 mhz 300 mhz fifo 128 x 32 197 mhz 235 mhz 128 x 64 188 mhz 266 mhz 256 x 16 208 mhz 248 mhz clock-to-out 4 ns 3.3 ns system clock 200 mhz 300 mhz ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 3 the eclipse-e logic cell structure presented in figure 2 is a dual register, multiple xor-based logic cell. it is designed for wide fan-in and multip le, simultaneous output functions. both registers share clk, set, and reset inputs. the second register ha s a two-to-one multiplexer controll ing its input. the register can be loaded from the nz output or directly from a dedicated input. note: the input pp is not an ?input? in the classical sense. it is a static input to the logic cell and selects which path (nz or ps) is used as an input to the q2z register. all other inputs are dynamic and can be connected to multiple routing channels. the complete logic cell c onsists of two six-input and gates, four two-input and gates, seven two-to-one multiplexers, and two d flip-flops with asynchronous set and reset controls. the cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). the high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. figure 2: eclipse-e logic cell qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 n p e2 d2 n s f1 f3 f5 f6 f2 f4 ps pp mp az oz qz n z fz q2z qc qr www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 4 ram modules the eclipse-e family includes up to 24 dual-port 2,304-bit ram modules for implementing ram, rom, and fifo functions. each module is user-c onfigurable into four different bloc k organizations and can be cascaded horizontally to increase their effective width, or vert ically to increase their e ffective depth as shown in figure 4 . figure 3: 2,304-bit ram module using the two ?mode? pins, designers can configure ea ch module into 128 x 18 and 256 x 9. the blocks are also easily cascadable to increase their effective width and/or depth (see figure 4 ) . figure 4: cascaded ram modules the ram modules are dual-port, with completely independent read and write ports and separate read and write clocks. the read ports support asynchro nous and synchronous operation, while the write ports support synchronous operation. each port has 18 da ta lines and 8 address lines, allowing word lengths of up to 18 bits and address spaces of up to 256 wo rds. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read operation (a syncrd input low), or as a flow-through enable for asynchronous read operation (asyncrd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. a similar technique can be used to cr eate depths greater than 256 words. in this case address signals higher than the msb are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher re ad address bits for the multiplexer select signals. the ram blocks can be loaded with da ta generated internally (typically for ram or fifo functions) or with data from an external prom (typically for rom functions). mode[1:0] wa[9:0] wd[17:0] we wclk a syncrd ra[9:0] rd[17:0] re rclk wdata rdata rdata waddr wdata raddr ram module (2,304 bits) ram module (2,304 bits) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 5 embedded computational unit (ecu) traditional programmable logic architec tures do not implement arithmetic fu nctions efficiently or effectively? these functions require high logic cell usage wh ile garnering only moderate performance results. the eclipse-e architecture allows for functionality abov e and beyond that achievable using programmable logic devices. by embedding a dynamically reconfigurable computational unit, the eclipse-e device can address various arithmetic functions efficiently. this approa ch offers greater performance and utilization than traditional programmable logic implementations. the embe dded block is implemented at the transistor level as shown in figure 5 . figure 5: ecu block diagram the eclipse-e ecu block ( table 3 ) is placed next to the sram circuitr y for efficient memory/instruction fetch and addressing for dsp algorithmic implementations. up to twelve 8-bit mac functions can be implemented pe r cycle for a total of up to 1.2 billion macs/s when clocked at 100 mhz. additional multip ly-accumulate functions can be implem ented in the prog rammable logic. table 3: eclipse-e ecu block device ecus ql6250e 10 ql6325e 12 a[0:15] b[0:15] sign2 sign1 cin s1 s2 s3 a b c d 3-4 decoder 8-bit multiplier 16-bit adder 17-bit register 2-1 mux 2-1 mux 3-1 mux q[16:0] clk reset dq 00 01 10 a[7:0] a[15:8] www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 6 the modes for the ecu block are dynamically re -programmable through the programmable logic. note: timing numbers in table 4 represent -8 worst case commercial conditions. phase locked loop (pll) information instead of requiring extra components, designers simply need to instantiate one of the pre-configured models (described in this section). the quic klogic built-in plls support a wider ra nge of frequencies than many other plls. these plls also have the abilit y to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than th e incoming clock frequency. when plls are cascaded, the clock signal must be routed off-chip through the pllpad_out pin prior to routing into another pll; internal routing cannot be used for cascading plls. figure 6 illustrates a quicklogic pll. figure 6: pll block diagram table 4: ecu mode select criteria instruction operation ecu performance a , -8 wcc a. t pd , t su and t co do not include routing paths in/out of the ecu block. s1 s2 s3 t pd t su t co 0 0 0 multiply 6.6 ns max 0 0 1 multiply-add 8.8 ns max 0 1 0 accumulate b b. internal feedback path in ecu re stricts max clk frequency to 238 mhz. 3.9 ns min 1.2 ns max 0 1 1 add 3.1 ns max 1 0 0 multiply (registered) c c. b [15:0] set to zero. 9.6 ns min 1.2 ns max 1 0 1 multiply- add (registered) 9.6 ns min 1.2 ns max 1 1 0 multiply - accumulate 9.6 ns min 1.2 ns max 1 1 1 add (registered) 3.9 ns min 1.2 ns max vco filter f in f out + - 1st quadrant 2nd quadrant 3rd quadrant 4th quadrant clock tree frequency divide frequency multiply 1 . _ . 2 . _ . 4 . _ . 4 . _ . 2 . _ . 1 . . _ pll bypass ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 7 f in represents a very stable high-frequency input clock and produces an accurate signal reference. this signal can either bypass the pll entirely, thus entering the cl ock tree directly, or it can pass through the pll itself. within the pll, a voltage-controlled oscillator (vco) is added to the circuit. the external f in signal and the local vco form a control loop. the vco is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in figure 6 ) can compare the two signals. if the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter ( figure 6 ). the charge pump generates an error voltage to bring the vco back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the vco. this new vco signal enters the clock tree to drive the chip's circuitry. f out represents the clock signal emerging from the output pad (the output signal pllpad_out is explained in table 6 ). the pll always drives the pllpad_out signal, regardless of whether the pll is configured for on-chip use. the pllpad_out will not oscillate if p ll_reset is asserted, or if the pll is powered down. most quicklogic products contain four plls. the pll presented in figure 6 controls the clock tree in the fourth quadrant of its fpga. quicklog ic plls compensate for the additiona l delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay thro ugh the feedback path. pll modes of operation quicklogic plls have eight modes of operation, base d on the input frequency and desired output frequency? table 5 indicates the features of each mode. note: ?hf? stands for ?high frequency? and ?lf? stands for ?low frequency.? the input frequency can range from 12.5 mhz to 440 mh z, while output frequenc y ranges from 25 mhz to 220 mhz. when adding plls to the top-level design, be sure that the pll mode matches the desired input and output frequencies. table 5: pll mode frequencies pll model output frequency input frequency range output frequency range pll_hf same as input 66 mhz?220 mhz 66 mhz?220 mhz pll_lf same as input 25 mhz?66 mhz 25 mhz?66 mhz pll_mult2hf 2x 33 mhz?110 mhz 66 mhz?220 mhz pll_mult2lf 2x 12.5 mhz?33 mhz 25 mhz?66 mhz pll_div2hf 1/2x 220 mhz?440 mhz 110 mhz?220 mhz pll_div2lf 1/2x 50 mhz?220 mhz 25 mhz?110 mhz pll_mult4 4x 12.5 mhz?50 mhz 50 mhz?200 mhz pll_div4 1/4x 100 mhz?440 mhz 25 mhz?110 mhz www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 8 pll signals table 6 summarizes the key signals in quicklogic plls. note: because pllclk_in and pll_reset signals have pll_inpad, and pllpad_out has outpad, you do not need to add additional pads to your design. i/o cell structure eclipse-e features a variety of distin ct i/o pins to maximize performance, functionality, and flexibility with bi-directional i/o pins and input-only pins. all input an d i/o pins are 1.8 v, 2.5 v, and 3.3 v tolerant and comply with the specific i/o standa rd selected. fo r single ended i/o standards, vccio specifies the input tolerance and the output drive. for voltage referenced i/o standards (e.g sstl), the voltage supplied to the inref pins in each bank specifies the input switch poin t. for example, the vccio pins must be tied to a 3.3 v supply to provide 3.3 v compliance. eclipse-e can also support the lvds and lvpecl i/o standards with the use of external resistors (see table 7 ). table 6: quicklogic pll signals signal name description pllclk_in input clock signal. pll_reset active high reset if pll_reset is assert ed, then clknet_out an d pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. onn_offchip this is a reserved signal. it can be connected to vcc or gnd. clknet_out out to inte rnal gates this signal bypasses the pll logic before driving the clock tree. note that this signal cannot be used in the same qua drant where the pll signal is used (pllclk_out). pllclk_out out from pll to internal gates this signal can drive the clock tree after going through the pll. pllpad_out out to off-chip this outgoing signal is used off-chip. the pllpad_out is always active, driving the pll-derived clock signal out through the pad. the pllpad_out will not oscillate if pll_reset is asserted, or if the pll is powered down. lock_detect active high lock detection signal note: for simulation purposes, this signal gets asserted after 10 clock cycles. however, it can take a maximum of 200 clock cycles to sync wi th the input cl ock upon release of the pll_reset signal. table 7: i/o standards and applications i/o standard reference voltage output voltage application lvttl n/a 3.3 v general purpose lv c m o s 2 5 n/a 2.5 v general purpose lvcmos18 n/a 1.8 v general purpose pci n/a 3.3 v pci bus applications gtl+ 1 n/a backplane sstl3 1.5 3.3 v sdram sstl2 1.25 2.5 v sdram ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 9 as designs become more complex and requirements more stringent, several application-specific i/o standards have emerged for specific applications. i/o standa rds for processors, memori es, and a variety of bus applications have become commonplace and a requirem ent for many systems. in addition, i/o timing has become a greater issue with specific requirements for setup, hold, clock to out, an d switching times. eclipse- e has addressed these new system re quirements and now includes a comp letely new i/o cell which consists of programmable i/os as well as a new cell structur e consisting of three registers?input, output, and oe. eclipse-e offers banks of programmable i/os that addre ss many of the bus standards that are popular today. as shown in figure 7 each bi-directional i/o pin is associated with an i/o cell which feat ures an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one output multiplexers. figure 7: eclipse-e i/o cell the bi-directional i/o pin options can be programmed for input, output, or bi-directional operation. as shown in figure 7 , each bi-directional i/o pin is associated with an i/o cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers. the select lines of the two-to-one multiplexers are static and must be connected to either vcc or gnd. for input functions, i/o pins can prov ide combinatorial, registered data, or both options simultaneously to the logic array. for combinatorial input operation, data is routed from i/o pins through the input buffer to the array logic. for registered input operation, i/o pins driv e the d input of input cell re gisters, allowing data to be captured with fast se t-up times without consuming internal logi c cell resources. the comparator and multiplexor in the input path allows for native support of i/o standards with reference points offset from traditional ground. for output functions, i/o pins can receive combinatorial or registered data from the logic array. for combinatorial output operation, data is routed from th e logic array through a multiplexer to the i/o pin. for registered output operation, the array logic drives the d input of the output cell regi ster which in turn drives e r q d r q d e r q d + - pad output enable register output register input register www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 10 the i/o pin through a multiplexer. the multiplexer allows either a combinatorial or a registered signal to be driven to the i/o pin. the addition of an output register will also decrease the tco. since the output register does not need to drive the ro uting the length of the outp ut path is also reduced. the three-state output buffer controls the flow of data from the array logic to the i/o pin and allows the i/o pin to act as an input and/or output. the buffer's output enable can be indi vidually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. the signal can also be either combinatorial or re gistered. this is identical to that of the flow for the output cell. for combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. the ioctrl pins can directly dr ive the oe and clk signals fo r all i/o cells within the same bank. for registered control operation, the array logic drives th e d input of the oe cell register which in turn drives the three-state control through a multiplexer. the multip lexer allows either a combinatorial or a registered signal to be driven to the three-state control. when i/o pins are unused, the oe cont rols can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. i/o cell registers are controlled by clock, clock enable , and reset signals, which can come from the regular routing resources, from one of the global networks, or from two ioctrl input pins per bank of i/o's. the clk and reset signals share common lines, while the cl ock enables for each regist er can be independently controlled. i/o interface support is programmable on a per bank basis. the two eclipse-e devices contain eight i/o banks. figure 8 illustrates the i/o bank configurations. each i/o bank is independent of other i/o banks an d each i/o bank has its own vccio and inref supply inputs. a mixture of different i/o standards can be used on the device; however, there is a limitation as to which i/o standards can be supporte d within a given bank. only standa rds that share a common vccio and inref can be shared within the same bank (e.g., pci and lvttl). figure 8: multiple i/o banks embedded ram blocks pll pll fabric embeded computational units embedded ram blocks pll pll vccio(f) inref(f) vccio(e) inref(e) vccio(d) inref(d) vccio(c) inref (c) inref(b) vccio(b) inref(a) vccio(a) inref(h) vccio(h) inref(g) vccio(g) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 11 programmable slew rate each i/o has programmable slew rate capability?the slew rate can be ei ther fast or slow. the slower rate can be used to reduce the sw itching times of each i/o. programmable weak pull-down a programmable weak pull-down resistor is available on each i/o. the i/o weak pull-down eliminates the need for external pull down resistors for used i/os as shown in figure 9 . the spec for pull-down current is maximum of 150 a under worst case condition. figure 9: programmable i/o weak pull-down i/o output logic pa d www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 12 clock networks global clocks there are a maximum of eight global clock networks in each eclipse-e device. global clocks can drive logic cells and i/o registers, ecus, and ram blocks in the devi ce. all global clocks have access to a quad net (local clock network) connection with a programmable conne ction to the logic cell?s register clock input. figure 10: global clock architecture quad-net network there are five quad-net local clock networks in each qu adrant for a total of 20 in a device. each quad-net is local to a quadrant. before driving th e columns clock buffers, the quad-net is driven by the output of a mux which selects between the clk pin input and an internally generate d clock source (see figure 11 ). figure 11: global clock structure quad net clk pin global clock net internally generated clock, or clock from general routing network global clock (clk) input quad-net clock network ff global clock buffer ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 13 dedicated clock there is one dedicated clock in the eclipse-e fami ly (ql6250e and ql6325e). this clock connects to the clock input of the logic cell and i/o registers, an d ram blocks through a hardwired connection and is multiplexed with the programmable clock input. the dedica ted clock provides a fast global network with low skew. users have the ability to select either the dedicated clock or the programmable clock ( figure 12 ). figure 12: dedicated clock circuitry within logic cell note: for more information on the clocking capabilitie s of eclipse-e fpgas, see quicklogic application note 68 at http://www.quicklogic.com /images/appnote68.pdf . i/o control and local hi-drives each bank of i/os has two input-only pins that can be programmed to drive the rst, clk, and en inputs of i/os in that bank. these input-only pins also serve as high drive inputs to a quadrant. these buffers can be driven by the internal logic both as an i/o control or high drive. for i/o constrained designs, these pins can be used for general purpose in puts. the performance of thes e resources is presented in table 8 . table 9 shows the total number of i/o control pins per device/package combination. table 8: i/o control network/local high-drive destination tt, 25 c, 2.5 v from pad from array i/o (far) 1.00 ns 1.14 ns i/o (near) 0.63 ns 0.78 ns skew 0.37 ns 0.36 ns table 9: i/o control pins per device/package combination device 208 pqfp 280 lfbga 484 bga ql6250e161616 ql6325e 16 16 16 programmable clock or general routing dedicated clock clk logic cell www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 14 programmable logic routing eclipse-e devices are engineered with six types of ro uting resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wire s, distributed networks, and default wires. short wires span the length of one logic cell, always in the vertic al direction. dual wires run horizontally and span the length of two logic cells. short and dual wires are pr edominantly used for local connections. default wires supply vcc and gnd (logic ?1? and logic ?0?) to each column of logic cells. quad wires have passive link interconne ct elements every fourth logic cell. as a result, these wires are typically used to implement intermediate length or medium fan-out nets. express lines run the length of the programmable logi c uninterrupted. each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. the resistance will also be lower because the express wires don' t require the use of ?pass? links. express wires provide higher performance for long routes or high fan-out nets. distributed networks are described in clock networks on page 12. these wires span the programmable logic and are driven by quad-net buffers. global power-on reset (por) the eclipse-e family of devices features a global power-on rese t. this reset is hardwired to all registers and resets them to logic ?0? upon power-up of the device . in quicklogic devices, the asynchronous reset input to flip-flops has priority over the se t input; therefore, the global por will reset all flip-flops during power-up. if you want to set the flip-flops to logic ?1?, you must assert the ?set? signal after the global por signal has been deasserted. figure 13: power-on reset low power mode quiescent power consumption of all eclipse-e devices can be reduced significantly by de-activating the charge pumps inside the architecture. by applying 3.3 v to the vpump pin, the internal charge pump is de- activated?this effectively reduces the static and dy namic power consumption of the device. the eclipse-e device is fully functional and operational in the low po wer mode. users who have a 3.3 v supply available in their system should take advantage of this low power fe ature by tying the vpump pin to 3.3 v. otherwise, if a 3.3 v supply is not available, this pin should be tied to ground. vcc power-on reset q xxxxxxx 0 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 15 joint test access group (jtag) information figure 14: jtag block diagram microprocessors and application specific integrated circuits (asics) pose many design challenges, one problem being the accessibility of test points. jtag fo rmed in response to this ch allenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run th ree required tests along with several user-defined tests. jtag tests allow users to reduce syst em debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. the 1149.1 standard requires the following three tests: ? extest instruction. the extest instruction performs a printed circuit board (pcb) interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap test data in (tdi) and te st data out (tdo) pins. boundary scan cells are preloaded with test patterns (through the sample/prelo ad instruction), and input boundary cells capture the input data for analysis. ? sample/preload instruction. the sample/preload instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed thro ugh a data scan operation, allowing users to sample the functional data entering and leaving the device. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 16 ? bypass instruction. the bypass instruction allows data to skip a device boundary scan entirely, so the data passes through the bypa ss register. the bypass instruction allows users to test a device without passing through other devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device withou t affecting the operation of the device. jtag bsdl support ? bsdl-boundary scan description language ? machine-readable data for test equipment to generate testing vectors and software ? bsdl files available for all device/p ackage combinations from quicklogic ? extensive industry support available and atvg (automatic test vector generation) security links there are several security links to disable reading logic from the array, and to disable jtag access to the device. programming these optional links completely disa bles access to the device from the outside world and provides an extra level of design security not possible in sram-based fpgas. the option to program these links is selectable through quickworks in the t ools/options/device programming window in spde. power-up loading link the flexibility link enables power-up loading of the embedded ram blocks. if the link is programmed, the power up loading state machine is activated during power-up of the device. the state machine communicates with an external eprom via the jtag pins to download memory contents into the on-chip ram. if the link is not programmed, power-up loadin g is not enabled and the jtag pins function as they normally would. the option to program this link is selectable throug h quickworks in the tools/options/device programming window in spde. for more information on power-up loading, see quicklogic application note 55 at http://www.quicklogic.com/images/appnote55.pdf . see the power-up loading power-up sequencing requirement for proper functionality in figure 15 . ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 17 figure 15: required power-up sequence when using power-up loading to use the power-up loading functi on, designers must ensure that v cc begins to ramp within a maximum of 2 ms of v ccio , v ded , v ded2 , and v pump . voltage v ccio v ded v ded2 v pump v cc time < 2 ms v cc v cc pll www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 18 electrical specifications dc characteristics the dc specifications are provided in table 10 through table 13 . table 10: absolute maximum ratings parameter value parameter value v cc pll, v cc voltage -0.5 v to 2.7v latch-up immunity 100 ma v ccio voltage -0.5 v to 4.0 v dc input current 20 ma inref voltage 0.5 v to vccio leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to v ccio +0.5 v laminate package (bga) storage temperature -55 c to + 125 c table 11: operating range symbol parameter military industrial commercial unit min max min max min max v cc pll, v cc supply voltage 2.3 2.7 2.3 2.7 2.3 2.7 v v ccio i/o input tolerance voltage 1.71 3.6 1.71 3.6 1.71 3.6 v ta ambient temperature -55 -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -6 speed grade 0.47 1.52 0.48 1.42 0.51 1.39 n/a -7 speed grade 0.46 1.35 0.47 1.27 0.50 1.24 n/a -8 speed grade 0.44 1.27 0.45 1.19 0.48 1.16 n/a ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 19 note: for pq208 package: all clk, ioctrl, and pllin pins are clamped to the vded rail. therefore, these pins can be driven up to vded. all jtag inputs are clamped to the vded2 rail. these jtag input pins can only be driven up to vded2. note: for pt280 and ps484 packages: all clk, ioctrl, and pllin pins are clamped to the vccio(c) rail. therefore, these pins can be driven up to vccio(c). all jtag inputs are clamped to the vded2 rail. these jtag input pins can only be driven up to vded2. table 12: dc characteristics symbol parameter conditions min max units i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd - 10 a c i i/o input capacitance a a. capacitance is sample tested only. clock pins are 12 pf maximum. --8pf c clock clock input capacitance - - 8 pf i os output short circuit current b b. only one output at a time. du ration should not exceed 30 seconds. v o = gnd v o = v cc -15 40 -180 210 ma ma i ded d.c. supply current on v ded - - - a i ref d.c. supply current on inref - -10 10 a i pd current on programmable pull-down v cc = 1.8 v - 50 a i ccio d.c. supply current on v ccio v ccio = 1.8 v v ccio = 2.5 v v ccio = 3.3 v - 10 10 20 a i pump d.c. supply current on v pump v pump = 3.3 v - - a i pll d.c. supply current on each v ccpll 2.5 v - 3 ma i cc d.c. supply current c, d c. for -6/-7/-8 commercial gr ade devices only. maximum i cc is 15 ma for all industrial grade devic es and 25 ma for all military devices. d. i cc is for current drawn by v cc and v ded . if any plls are used, see table 12 for current drawn by each pll. v pump = 0 v v pump = 3.3 v - - 10 - ma ma table 13: dc input and output levels a a. the data provided in table 13 are jedec and pci specifications?quicklogic devic es either meet or exceed these requirements. for data specific to quicklogic i/os, see table 18 through table 23 and figure 34 through figure 38 . inref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lvttl n/a n/a -0.3 0.8 2.2 v ccio + 0.3 0.4 2.4 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 v ccio + 0.3 0.7 1.7 2.0 -2.0 lv c m o s 1 8 n/a n/a -0.3 0.63 1.2 v ccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x v ccio 0.6 x v ccio v ccio + 0.5 0.1 x v ccio 0.9 x v ccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 v ccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 1.10 1.90 8 -8 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 20 figure 16 through figure 19 show the vil and vih characteristics for i/o and clock pins. figure 16: vil maximum for i/o figure 17: vih minimum for i/o vilmax for io 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71 v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v vihmin for io 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage 1.71 v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 21 figure 18: vil maximum for clock pins figure 19: vih minimum for clock pins vilmax for clock pins 0 0.5 1 1.5 2 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v vihmin for clock pins 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71 v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 22 figure 20 through figure 24 show the output drive characteristics for the i/os across va rious voltages and temperatures. figure 20: drive current at vccio = 1.71 v figure 21: drive current at vccio = 1.8 v drive current @ vccio = 1.71 v 0 5 10 15 20 25 30 35 0 0.2 0 .4 0 .6 0 .8 1 1.2 1.4 1 .6 1. 71 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c drive current @ vccio = 1.8 v 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 output voltage (v) drive current (ma ) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 23 figure 22: drive current at vccio = 2.5 v figure 23: drive current at vccio = 3.3 v drive current @ vccio = 2.5v 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c drive current @ vccio = 3.3v 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.3 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 24 figure 24: drive current at vccio = 3.6 v drive current @ vccio = 3.6v 0 20 40 60 80 100 120 140 00.511.522.533.33.6 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 25 ac characteristics* *at v cc = 2.5 v, ta = 25c, worst case corner, speed grade = -6 (k = 1.01). the ac specifications are provided from table 14 to table 23 . logic cell diagrams and waveforms are provided from figure 25 to figure 38 . figure 25: eclipse-e logic cell table 14: logic cell delays symbol parameter value min max t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output 0.28 ns 0.98 ns t su setup time: time the synchronous input of t he flip-flop must be stable before the active clock edge 0.10 ns 0.25 ns t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns 0 ns t co clock-to-out delay: the amount of time ta ken by the flip-flop to output after the active clock edge. 0.22 ns 0.52 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns 0.46 ns t cwlo clock low time: required minimum time that the clock stays low 0.46 ns 0.46 ns t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) 0.69 ns 0.69 ns t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) 1.09 ns 1.09 ns t sw set width: time that the set signa l must remain high/low 0.3 ns 0.3 ns t rw reset width: time th at the reset signal must remain high/low 0.3 ns 0.3 ns www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 26 figure 26: logic cell flip-flop figure 27: logic cell flip-flop timings?first waveform figure 28: logic cell flip-flop timings?second waveform set d clk reset q set reset q clk t cwhi (min) t cwlo (min) t reset t rw t set t sw clk d q t su t hl t co ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 27 figure 29: eclipse-e global clock structure note: when using a pll, t pgck and t bgck are effectively zero due to delay adjustment by phase locked loop feedback path. figure 30: global clock structure timing elements table 15: eclipse-e tree clock delay clock segment parameter value min max t pgck global clock pin delay to quad net - 1.92 ns t bgck global clock tree delay (quad net to flip-flop) - 0.28 ns t dpd dedicated clock pad - 1.7 ns t gskew global delay clock skew - 0.1 ns t dskew dedicated clock skew - 0.05 ns quad net internally generated clock, or clock from general routing network global clock (clk) input quad-net clock network ff global clock buffer www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 28 figure 31: ram module table 16: ram cell synchronous write timing symbol parameter value min max ram cell synchronous write timing t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.47 ns - t hwa wa hold time to wclk: time the writ e address must be stable after the active edge of the write clock 0 ns - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.48 ns - t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns - t swe we setup time to wclk: time the writ e enable must be stable before the active edge of the write clock 0 ns - t hwe we hold time to wclk: time the wr ite enable must be stable after the active edge of the write clock 0 ns - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 3.79 ns wa wd we wclk re rclk ra rd ram mod ule [9:0] [17:0] [9:0] [17:0] asyncrd ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 29 figure 32: ram cell synchronous write timing table 17: ram cell synchronous and asynchronous read timing symbol parameter value min max ram cell synchronous read timing t sra ra setup time to rclk: time the r ead address must be stable before the active edge of the read clock 0.43 ns - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns - t sre re setup time to wclk: time the read enable must be stable before the active edge of the read clock 0.21 ns - t hre re hold time to wclk: time the read enable must be stable after the active edge of the read clock 0 ns - t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 2.25 ns ram cell asynchronous read timing r pdrd ra to rd: time between when the read address is input and when the data is output - 1.99 ns t swa t swd t swe t hwa t hwd t hwe t wcrd old data new data wclk wa wd we rd www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 30 figure 33: ram cell synchronous & asynchronous read timing figure 34: eclipse-e cell i/o t sra t hra rclk ra t sre t hre t rcrd old data new data re rd r pdrd e r q d r q e r q d + - pad output enable register output register input register d ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 31 figure 35: eclipse-e input register cell table 18: i/o input register cell timing symbol parameter value min max t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 2.15 ns - t ihl input register hold time: time the synchronous input of the flip-fl op must be stable after the active clock edge 0 ns - t ico input register clock-to-out: time taken by the flip-flop to output after the active clock edge - 0.3 ns t irst input register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low) - 0.82 ns t iesu input register clock enable setup time: time ?enable? must be stable before the active clock edge 0.4 ns - t ieh input register clock enable hold time: time ?enable? must be stable after the active clock edge 0 ns - pad t isu t sid + - q e d r www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 32 figure 36: eclipse-e input register cell timing table 19: i/o input buffer delays symbol parameter value to get the total input delay add this delay to t isu min max t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.82 ns t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.82 ns t sid (lvcmos18) lvcmos18 input delay: low voltage cmos for 1.8 v applications - - t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.94 ns t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.94 ns t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.94 ns t sid (pci) pci input delay: peripheral component interconnect for 3.3 v - 0.82 ns r clk d q isu ihl ico iesu ieh irst e t t t t t t ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 33 figure 37: eclipse-e output register cell table 20: eclipse-e i/o cell output timing symbol parameter value (ns) output register cell only slow slew max fast slew max t outlh output delay low to high (90% of h) 4.0 2.95 t outhl output delay high to low (10% of l) 3.5 2.49 t pzh output delay tri-state to high (90% of h) 4.96 2.93 t pzl output delay tri-state to low (10% of l) 4.87 2.84 t phz output delay high to tri-state 5.8 3.62 t plz output delay low to tri-state 5.58 3.4 t cop clock-to-out delay (does not in clude clock tree delays) 5.49 3.3 pad output register www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 34 figure 38: eclipse-e output register cell timing table 21: output slew rates @ v ccio = 3.3 v fast slew slow slew rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns table 22: output slew rates @ v ccio = 2.5 v fast slew slow slew rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns table 23: output slew rates @ v ccio = 1.8 v fast slew slow slew rising edge - v/ns - v/ns falling edge - v/ns - v/ns l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 35 package thermal characteristics thermal resistance equations: jc = (t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 150o c. to calculate the maximum power dissipation for a device package look up ja from table 24 , pick an appropriate t amax and use: p max = (150o c - t amax )/ ja table 24: package thermal characteristics device package description ja (o c/w) package code package type pin count 0 lfm 200 lfm 400 lfm ql6250e ps pbga 484 26.6 24.1 21.8 pt lf-pbga 280 34 13.6 29.9 pq pqfp 208 32 28 26.5 ql6325e ps pbga 484 26.6 24.1 21.8 pt lfbga 280 34 13.6 29.9 pq pqfp 208 32 28 26.5 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 36 kv and kt graphs figure 39: voltage factor vs. supply voltage figure 40: temperature factor vs. operating temperature voltage factor vs supply voltage 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 2.25 2.35 2.45 2.5 2.55 2.65 2.75 supply voltage (v) kv kv temperature factor vs. operating temperature 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 -60 -55 -40 0 25 85 125 130 junction temperature (c) kt kt ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 37 power vs. operating frequency the basic power equation which best mo dels power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where: lc is the total number of logic cells in the design ckbf = # of clock buffers clbf = # of column clock buffers ckld = # of loads connected to the column clock buffers ram = # of ram blocks pll = # of plls inp is the number of input pins outp is the number of output pins note: to learn more about power consumption, see quicklogic application note 60 at http://www.quicklogic.com /images/appnote60.pdf . www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 38 power-up sequencing figure 41: power-up sequencing when powering up a device, the v cc pll/v cc /v ccio /v ded /v ded2 rails must take 400 s or longer to reach the maximum value (refer to figure 41 ). note: ramping v cc pll, v cc , v ccio , v pump , v ded , or v ded2 faster than 400 s can cause the device to behave improperly. for users with a limited power budget, ensure v ccio , v ded , v ded2 , and v pump are within 500 mv of v cc when ramping up the power supplies. voltage v ccio v ded v ded2 v pump v cc |v ccio , v ded , v ded2 , v pump - v cc | max time 400 us v cc v cc pll ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 39 pq208 pin descriptions table 25: pq208 pin descriptions pin directio n function description jtag pin descriptions tdi/rsi i test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to vded2 if unused trstb/rro i/0 active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms i test mode select for jtag hold high during normal operation. connect to vded2 if not used for jtag tck i test clock for jtag hold high or low during normal operation. connect to vded2 or gnd if not used for jtag tdo/rco o test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization. the output voltage drive is specified by vded. dedicated pin descriptions clk i global clock network pin low skew global clock. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. the voltage tolerance of this pin is specified by vded. i/o(a) i/o input/output pin the i/o pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-dir ectional pin. the a inside the parenthesis means that the i/o is located in bank a. if an i/o is not used, spde (quickworks tool) provides the option of tying that pin to gnd, vcc , or tristate. vcc i power supply pin connect to 2.5 v supply. vccio(a) i input voltage tolerance/drive pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the a inside the parenthesis means that vccio is located in bank a. every i/o pin in bank a will be tolerant of vccio input signals and will drive vccio level output signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. gnd i ground pin connect to ground. pllin i pll clock input clock input for pll. the voltage tolerance of this pin is specified by vded. dedclk i dedicated clock pin very low skew global clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g., ram, flip flops). the voltage tolerance of this pin is specified by vded. gndpll i ground pin for pll connect to gnd. www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 40 inref(a) i differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in table 13 for the appropriate standard. the a inside the parenthesis means t hat inref is located in bank a. this pin should be tied to gnd if voltage referenced standards are not used. pllout o pll output pin dedicated pll output pin. mu st be left unconnected if the pll is not driven off chip. pllo ut pin is driven by vccio. for a list of each pllout pin and the vccio pin that powers it see table 27 . ioctrl(a) i highdrive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-fl ops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. the a inside the parenthesis means that ioctrl is located in bank a. there is an internal pulldown resistor to gnd on this pin. this pin should be tied to gnd if it is not used. for backwards compatibility with eclipse and eclipseplus, it can be tied to vded or gnd. if tied to vded, it will draw no more than 20 a per ioctrl pin due to the pulldown resistor. the voltage tolerance of this pin is specified by vded. vpump i charge pump disable this pin disables the internal charge pump for lower static power consumption. to disable the charge pump, connect vpump to 3.3 v. if the disable charge pump feature is not used, connect vpump to gnd. for backwards compatibility with eclipse and eclipseplus devices, connect vpump to gnd. vded i voltage tolerance for clocks, tdo jtag output, and ioctrl this pin specifies the input voltage tolerance for clk, dedclk, pllin, and ioctrl dedicated input pins, as well as the output voltage drive tdo jtag pins. if the plls are used, vded must be 2.5 v or 3.3 v. the legal range for vded is between 1.71 v and 3.6 v. for backwards compatibility with eclipse and eclipseplus devices, connect vded to 2.5 v. vded2 i voltage tolerance for jtag pins (tdi, tms, tck, and trstb) these pins specify the input vo ltage tolerance for the jtag input pins. the legal range for vded2 is between 1.71 v and 3.6 v. these do not specify ou tput voltage of the jtag output, tdo. refer to the vded pin section for specifying the jtag output voltage. vded2 must be equal to or greater than vded. vccpll i power supply pin for pll connect to 2.5 v supply. even if your design does not utilize the plls, you must connect vccpll to 2.5 v. pll_reset i pll reset pin if pll_reset is asserted, then clknet_out and pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. if a pll module is not used, then the associated pllrst ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 41 pt280 and ps484 pin descriptions table 26: pt280 and ps484 pin descriptions pin directio n function description jtag pin descriptions tdi/rsi i test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to vded2 if unused trstb/rro i/0 active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms i test mode select for jtag hold high during normal operation. connect to vded2 if not used for jtag tck i test clock for jtag hold high or low during normal operation. connect to vded2 or gnd if not used for jtag tdo/rco o test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization. the output voltage drive is specified by vccio(c). dedicated pin descriptions clk i global clock network pin low skew global clock. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. the voltage tolerance of this pin is specified by vccio(c). dedclk i dedicated clock pin very low skew global clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g., ram, flip flops). the voltage tolerance of this pin is specified by vccio(c). gnd i ground pin connect to ground. gndpll i ground pin for pll connect to gnd. inref(a) i differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in table 13 for the appropriate standard. the a inside the parenthesis means t hat inref is located in bank a. this pin should be tied to gnd if voltage referenced standards are not used. i/o(a) i/o input/output pin the i/o pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-dir ectional pin. the a inside the parenthesis means that the i/o is located in bank a. if an i/o is not used, spde (quickworks tool) provides the option of tying that pin to gnd, vcc , or tristate. www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 42 ioctrl(a) i highdrive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-fl ops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. the a inside the parenthesis means that ioctrl is located in bank a. there is an internal pulldown resistor to gnd on this pin. this pin should be tied to gnd if it is not used. for backwards compatibility with eclipse and eclipseplus, it can be tied to vccio(c) or gnd. if tied to vccio(c), it will draw no more than 20 a per ioctrl pin due to the pulldown resistor. the voltage tolerance of this pin is specified by vccio(c). pllin i pll clock input clock input for pll. the voltage tolerance of this pin is specified by vccio(c). pllout o pll output pin dedicated pll output pin. mu st be left unconnected if the pll is not driven off chip. pllo ut pin is driven by vccio. for a list of each pllout pin and the vccio pin that powers it see table 27 . vcc i power supply pin connect to 2.5 v supply. vccio(c) i voltage tolerance for clocks, tdo jtag output, and ioctrl. input voltage tolerance/drive pin. this pin specifies the input voltage tolerance for clk, dedclk, pllin, and ioctrl dedicated input pins, as well as the output voltage drive tdo jtag pins. if the plls are used, vccio(c) must be 2.5 v or 3.3 v. the legal range for vccio(c) is between 1.71 v and 3.6 v. this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the c inside the parenthesis means that vccio is located in bank c. every i/o pin in bank c will be tolerant of vccio input signals and will drive vccio level output signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. vccio(a), vccio(b), vccio(d), vccio(e), vccio(f), vccio(g), vccio(h) i input voltage tolerance/drive pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. as an example, the a inside the parenthesis means that vccio is located in bank a. every i/o pin in bank a will be tolerant of vccio input signals and will drive vccio level output signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. vccpll i power supply pin for pll connect to 2.5 v supply. even if your design does not utilize the plls, you must connect vccpll to 2.5 v. pll_reset i pll reset pin if pll_reset is asserted, then clknet_out and pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. if a pll module is not used, then the associated pllrst ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 43 vded i no connect this pin may be left unconnected. see pin vccio(c) for more information. vded2 i voltage tolerance for jtag pins (tdi, tms, tck, and trstb) these pins specify the input vo ltage tolerance for the jtag input pins. the legal range for vded2 is between 1.71 v and 3.6 v. these do not specify ou tput voltage of the jtag output, tdo. refer to the vccio(c) pin section for specifying the jtag output voltage. vded2 must be equal to or greater than vccio(c). vpump i charge pump disable this pin disables the internal charge pump for lower static power consumption. to disable the charge pump, connect vpump to 3.3 v. if the disable charge pump feature is not used, connect vpump to gnd. for backwards compatibility with eclipse and eclipseplus devices, connect vpump to gnd. table 27: pllout pin supply voltage pllout vccio pllout(0) vccio(e) pllout(1) vccio(b) pllout(2) vccio(a) pllout(3) vccio(f) table 26: pt280 and ps484 pin descriptions (continued) pin directio n function description www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 44 figure 42: i/o banks with relevant pins recommended unused pin terminations for eclipse-e devices all unused, general purpose i/o pins ca n be tied to vcc, gnd, or hiz (h igh impedance) inte rnally using the configuration editor. this option is given in the botto m-right corner of the placement window. to use the placement editor, choose constraint > fix placement in the option pull-down menu of spde. io bank a io bank b v ccio (a) inref(a) ioctrl(a) io(a) v ccio (a) inref(a) ioctrl(a) io(a) io bank c io bank d v ccio (c) inref(c) ioctrl(c) io(c) v ccio (d) inref(d) ioctrl(d) io(d) io bank f io bank e v ccio (f) inref(f) ioctrl(f) io(f) v ccio (e) inref(e) ioctrl(e) io(e) io bank h io bank g (h) inref(h) ioctrl(h) io(h) v ccio v ccio (g) inref(g) ioctrl(g) io(g) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 45 the rest of the pq208 pins should be terminated at the board level in the manner presented in table 28 . the rest of the pt280 and ps484 pins sh ould be terminated at the board level in th e manner presented in table 29 . table 28: pq208 recommended unused pin terminations signal name recommended termination pllout www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 46 ql6250e - 208 pqfp pinout diagram eclipse-e ql6250e-6pq208c ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 47 ql6250e - 208 pqfp pinout table table 31: ql6250e - 208 pqfp pinout table pin function pin function pin function pin function pin function 1 pllrst(3) 43 i/o(b) 85 i/o(d) 127 clk(5)/pllin(3) 169 ioctrl(g) 2 vccpll(3) 44 vccio(b) 86 vcc 128 clk(6) 170 inref(g) 3 gnd 45 i/o(b) 87 i/o(d) 129 vded 171 ioctrl(g) 4 gnd 46 vcc 88 i/o(d) 130 clk(7) 172 i/o(g) 5 i/o(a) 47 i/o(b) 89 vcc 131 vcc 173 i/o(g) 6 i/o(a) 48 i/o(b) 90 i/o(d) 132 clk(8) 174 i/o(g) 7 i/o(a) 49 gnd 91 i/o(d) 133 tms 175 vcc 8 vccio(a) 50 tdo 92 ioctrl(d) 134 i/o(f) 176 i/o(g) 9 i/o(a) 51 pllout(1) 93 inref(d) 135 i/o(f) 177 vccio(g) 10 i/o(a) 52 gndpll(2) 94 ioctrl(d) 136 i/o(f) 178 gnd 11 ioctrl(a) 53 gnd 95 i/o(d) 137 gnd 179 i/o(g) 12 vcc 54 vccpll(2) 96 i/o(d) 138 vccio(f) 180 i/o(g) 13 inref(a) 55 pllrst(2) 97 i/o(d) 139 i/o(f) 181 i/o(g) 14 ioctrl(a) 56 vded 98 vccio(d) 140 i/o(f) 182 vcc 15 i/o(a) 57 i/o(c) 99 i/o(d) 141 i/o(f) 183 tck 16 i/o(a) 58 gnd 100 i/o(d) 142 i/o(f) 184 vded2 17 i/o(a) 59 i/o(c) 101 vpump 143 i/o(f) 185 i/o(h) 18 i/o(a) 60 vccio(c) 102 pllout(0) 144 ioctrl(f) 186 i/o(h) 19 vccio(a) 61 i/o(c) 103 gnd 145 inref(f) 187 i/o(h) 20 i/o(a) 62 i/o(c) 104 gndpll(1) 146 vcc 188 gnd 21 gnd 63 i/o(c) 105 pllrst(1) 147 ioctrl(f) 189 vccio(h) 22 i/o(a) 64 i/o(c) 106 vccpll(1) 148 i/o(f) 190 i/o(h) 23 tdi 65 i/o(c) 107 i/o(e) 149 i/o(f) 191 i/o(h) 24 clk(0) 66 i/o(c) 108 gnd 150 vccio(f) 192 ioctrl(h) 25 clk(1) 67 ioctrl(c) 109 i/o(e) 151 i/o(f) 193 i/o(h) 26 vcc 68 inref(c) 110 i/o(e) 152 i/o(f) 194 inref(h) 27 clk(2)/pllin(2) 69 ioctrl(c) 111 vccio(e) 153 gnd 195 vcc 28 clk(3)/pllin(1) 70 i/o(c) 112 i/o(e) 154 i/o(f) 196 ioctrl(h) 29 vded 71 i/o(c) 113 vcc 155 pllout(3) 197 i/o(h) 30 clk(4) dedclk pllin(0) 72 vccio(c) 114 i/o(e) 156 gndpll(0) 198 i/o(h) 31 i/o(b) 73 i/o(c) 115 i/o(e) 157 gnd 199 i/o(h) 32 i/o(b) 74 i/o(c) 116 i/o(e) 158 vccpll(0) 200 i/o(h) 33 gnd 75 gnd 117 ioctrl(e) 159 pllrst(0) 201 i/o(h) 34 vccio(b) 76 vcc 118 inref(e) 160 gnd 202 i/o(h) 35 i/o(b) 77 i/o(c) 119 ioctrl(e) 161 i/o(g) 203 vccio(h) 36 i/o(b) 78 trstb 120 i/o(e) 162 vccio(g) 204 gnd 37 i/o(b) 79 vded2 121 i/o(e) 163 i/o(g) 205 i/o(h) 38 i/o(b) 80 i/o(d) 122 vccio(e) 164 i/o(g) 206 pllout(2) 39 ioctrl(b) 81 i/o(d) 123 gnd 165 vcc 207 gnd 40 inref(b) 82 i/o(d) 124 i/o(e) 166 i/o(g) 208 gndpll(3) 41 ioctrl(b) 83 gnd 125 i/o(e) 167 i/o(g) 42 i/o(b) 84 vccio(d) 126 i/o(e) 168 i/o(g) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 48 ql6250e - 280 lfbga pinout diagram top bottom eclipse-e ql6250e-6pt280c pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 49 ql6250e - 280 lfbga pinout table table 32: ql6250e - 280 lfbga pinout table ball function ball function ball function ball function ball function ball function a1 pllout(3) c10 clk(5)/ pllin(3) e19 ioctrl(d) k16 i/o(c) r4 i/o(h) u13 i/o(b) a2 gndpll(0) c11 vccio(e) f1 inref(g) k17 i/o(d) r5 gnd u14 ioctrl(b) a3 i/o(f) c12 i/o(e) f2 ioctrl(g) k18 i/o(c) r6 gnd u15 vccio(b) a4 i/o(f) c13 i/o(e) f3 i/o(g) k19 trstb r7 vcc u16 i/o(b) a5 i/o(f) c14 i/o(e) f4 i/o(g) l1 i/o(h) r8 vcc u17 tdo a6 ioctrl(f) c15 vccio(e) f5 gnd l2 i/o(h) r9 gnd u18 pllrst(2) a7 i/o(f) c16 i/o(e) f15 vcc l3 vccio(h) r10 gnd u19 i/o(b) a8 i/o(f) c17 i/o(e) f16 ioctrl(d) l4 i/o(h) r11 vcc v1 pllout(2) a9 i/o(f) c18 i/o(e) f17 i/o(d) l5 vcc r12 vcc v2 gndpll(3) a10 clk(7) c19 i/o(e) f18 i/o(d) l15 gnd r13 vcc v3 gnd a11 i/o(e) d1 i/o(g) f19 i/o(d) l16 i/o(c) r14 vded v4 i/o(a) a12 i/o(e) d2 i/o(g) g1 i/o(g) l17 vccio(c) r15 gnd v5 i/o(a) a13 i/o(e) d3 i/o(f) g2 i/o(g) l18 i/o(c) r16 i/o(c) v6 ioctrl(a) a14 ioctrl(e) d4 i/o(f) g3 ioctrl(g) l19 i/o(c) r17 vccio(c) v7 i/o(a) a15 i/o(e) d5 i/o(f) g4 i/o(g) m1 i/o(h) r18 i/o(c) v8 i/o(a) a16 i/o(e) d6 i/o(f) g5 vcc m2 i/o(h) r19 i/o(c) v9 i/o(a) a17 i/o(e) d7 i/o(f) g15 vcc m3 i/o(h) t1 i/o(h) v10 clk(1) a18 pllrst(1) d8 i/o(f) g16 i/o(d) m4 i/o(h) t2 i/o(h) v11 clk(4)/ dedclk/ pllin(0) a19 gnd d9 clk(8) g17 i/o(d) m5 vcc t3 i/o(a) v12 i/o(b) b1 pllrst(0) d10 i/o(e) g18 i/o(d) m15 vded t4 i/o(a) v13 i/o(b) b2 gnd d11 i/o(e) g19 i/o(d) m16 inref(c) t5 i/o(a) v14 inref(b) b3 i/o(f) d12 i/o(e) h1 i/o(g) m17 i/o(c) t6 ioctrl(a) v15 i/o(b) b4 i/o(f) d13 inref(e) h2 i/o(g) m18 i/o(c) t7 i/o(a) v16 i/o(b) b5 i/o(f) d14 i/o(e) h3 i/o(g) m19 i/o(c) t8 i/o(a) v17 i/o(b) b6 inref(f) d15 i/o(e) h4 i/o(g) n1 ioctrl(h) t9 i/o(a) v18 gndpll(2) b7 i/o(f) d16 i/o(d) h5 vcc n2 i/o(h) t10 i/o(a) v19 gnd b8 i/o(f) d17 i/o(d) h15 vcc n3 i/o(h) t11 clk(3)/ pllin(1) w1 gnd b9 tms d18 i/o(d) h16 vded2 n4 i/o(h) t12 i/o(b) w2 pllrst(3) b10 clk(6) d19 i/o(d) h17 i/o(d) n5 vcc t13 i/o(b) w3 i/o(a) b11 i/o(e) e1 i/o(g) h18 i/o(d) n15 vcc t14 i/o(b) w4 i/o(a) b12 i/o(e) e2 i/o(g) h19 i/o(d) n16 i/o(c) t15 i/o(b) w5 i/o(a) b13 ioctrl(e) e3 vccio(g) j1 i/o(g) n17 i/o(c) t16 i/o(b) w6 i/o(a) b14 i/o(e) e4 i/o(f) j2 i/o(g) n18 ioctrl(c) t17 vccpll(2) w7 i/o(a) b15 i/o(e) e5 gnd j3 vccio(g) n19 ioctrl(c) t18 i/o(b) w8 i/o(a) b16 i/o(e) e6 vcc j4 i/o(g) p1 i/o(h) t19 i/o(b) w9 tdi b17 vccpll(1) e7 vcc j5 gnd p2 i/o(h) u1 i/o(a) w10 clk(2)/ pllin(2) b18 gndpll(1) e8 vded j15 vcc p3 ioctrl(h) u2 i/o(a) w11 i/o(b) b19 pllout(0) e9 vcc j16 i/o(c) p4 inref(h) u3 vccpll(3) w12 i/o(b) c1 i/o(f) e10 gnd j17 vccio(d) p5 vcc u4 i/o(a) w13 i/o(b) c2 vccpll(0) e11 gnd j18 i/o(d) p15 gnd u5 vccio(a) w14 ioctrl(b) c3 i/o(f) e12 vcc j19 i/o(d) p16 i/o(c) u6 inref(a) w15 i/o(b) c4 i/o(f) e13 vcc k1 vded2 p17 i/o(c) u7 i/o(a) w16 i/o(b) c5 vccio(f) e14 gnd k2 tck p18 i/o(c) u8 i/o(a) w17 i/o(b) c6 ioctrl(f) e15 vpump k3 i/o(g) p19 i/o(c) u9 vccio(a) w18 i/o(b) c7 i/o(f) e16 i/o(d) k4 i/o(g) r1 i/o(h) u10 clk(0) w19 pllout(1) c8 i/o(f) e17 vccio(d) k5 gnd r2 i/o(h) u11 vccio(b) c9 vccio(f) e18 inref(d) k15 gnd r3 vccio(h) u12 i/o(b) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 50 ql6250e - 484 pbga pinout diagram top bottom eclipse-e ql6250e-6ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner pin a1 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 51 ql6250e - 484 pbga pinout table table 33: ql6250e - 484 pbga pinout table ball function ball function ball function ball function ball function ball function a1 nc c1 nc e1 ioctrl(a) g1 nc j1 i/o(a) l1 clk(4)/ dedclk/ pllin(0) a2 pllrst(3) c2 i/o(a) e2 i/o(a) g2 nc j2 i/o(a) l2 clk(0) a3 i/o(a) c3 vccpll(3) e3 i/o(a) g3 i/o(a) j3 i/o(a) l3 clk(2)/pllin(2) a4 i/o(a) c4 pllout(2) e4 i/o(a) g4 i/o(a) j4 i/o(a) l4 i/o(a) a5 i/o(a) c5 i/o(a) e5 nc g5 i/o(a) j5 i/o(a) l5 i/o(a) a6 nc c6 nc e6 i/o(h) g6 i/o(a) j6 i/o(a) l6 i/o(a) a7 i/o(h) c7 i/o(h) e7 nc g7 gnd j7 i/o(a) l7 gnd a8 ioctrl(h) c8 nc e8 i/o(h) g8 i/o(h) j8 vcc l8 gnd a9 i/o(h) c9 ioctrl(h) e9 i/o(h) g9 i/o(h) j9 gnd l9 gnd a10 nc c10 nc e10 i/o(h) g10 nc j10 vcc l10 gnd a11 nc c11 i/o(h) e11 vded2 g11 i/o(g) j11 vcc l11 gnd a12 tck c12 nc e12 i/o(g) g12 gnd j12 gnd l12 gnd a13 i/o(g) c13 i/o(g) e13 i/o(g) g13 nc j13 vcc l13 gnd a14 i/o(g) c14 nc e14 nc g14 nc j14 gnd l14 vcc a15 i/o(g) c15 i/o(g) e15 ioctrl(g) g15 i/o(g) j15 vcc l15 vcc a16 nc c16 i/o(g) e16 i/o(g) g16 vpump j16 i/o(f) l16 clk(6) a17 i/o(g) c17 nc e17 inref(g) g17 vccio(f) j17 vccio(f) l17 vccio(f) a18 i/o(g) c18 i/o(g) e18 nc g18 i/o(f) j18 i/o(f) l18 i/o(f) a19 i/o(f) c19 i/o(f) e19 i/o(f) g19 i/o(f) j19 i/o(f) l19 clk(8) a20 gnd c20 gndpll(0) e20 i/o(f) g20 i/o(f) j20 i/o(f) l20 i/o(f) a21 pllout(3) c21 i/o(f) e21 nc g21 inref(f) j21 i/o(f) l21 nc a22 i/o(f) c22 i/o(f) e22 i/o(f) g22 i/o(f) j22 i/o(f) l22 i/o(f) b1 i/o(a) d1 i/o(a) f1 i/o(a) h1 i/o(a) k1 tdi m1 i/o(b) b2 gnd d2 i/o(a) f2 inref(a) h2 i/o(a) k2 i/o(a) m2 i/o(b) b3 gndpll(3) d3 i/o(a) f3 nc h3 i/o(a) k3 i/o(a) m3 i/o(b) b4 gnd d4 i/o(a) f4 i/o(a) h4 i/o(a) k4 i/o(a) m4 clk(3)/pllin(1) b5 i/o(a) d5 i/o(a) f5 i/o(a) h5 ioctrl(a) k5 i/o(a) m5 nc b6 i/o(h) d6 i/o(h) f6 vccio(a) h6 vccio(a) k6 vccio(a) m6 vccio(b) b7 i/o(h) d7 nc f7 vccio(h) h7 i/o(h) k7 nc m7 clk(1) b8 inref(h) d8 i/o(h) f8 i/o(h) h8 gnd k8 vcc m8 vcc b9 i/o(h) d9 nc f9 vccio(h) h9 vcc k9 vcc m9 vcc b10 i/o(h) d10 i/o(h) f10 i/o(h) h10 vcc k10 gnd m10 gnd b11 i/o(h) d11 i/o(h) f11 vccio(h) h11 vded k11 gnd m11 gnd b12 nc d12 i/o(g) f12 vccio(g) h12 gnd k12 gnd m12 gnd b13 nc d13 i/o(g) f13 i/o(g) h13 vcc k13 gnd m13 gnd b14 nc d14 i/o(g) f14 vccio(g) h14 vcc k14 vcc m14 gnd b15 nc d15 ioctrl(g) f15 nc h15 gnd k15 vcc m15 gnd b16 i/o(g) d16 i/o(g) f16 vccio(g) h16 i/o(f) k16 nc m16 gnd b17 i/o(g) d17 i/o(g) f17 nc h17 i/o(f) k17 i/o(f) m17 i/o(e) b18 i/o(g) d18 i/o(f) f18 i/o(f) h18 nc k18 i/o(f) m18 i/o(e) b19 pllrst(0) d19 vccpll(0) f19 i/o(f) h19 i/o(f) k19 nc m19 i/o(e) b20 i/o(f) d20 i/o(f) f20 ioctrl(f) h20 i/o(f) k20 i/o(f) m20 clk(7) b21 i/o(f) d21 i/o(f) f21 i/o(f) h21 i/o(f) k21 i/o(f) m21 clk(5)/pllin(3) b22 i/o(f) d22 i/o(f) f22 ioctrl(f) h22 nc k22 nc m22 tms www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 52 n1 nc p16 i/o(e) t9 nc v2 i/o(b) w17 nc aa10 i/o(c) n2 i/o(b) p17 nc t10 trstb v3 i/o(b) w18 i/o(e) aa11 i/o(c) n3 i/o(b) p18 i/o(e) t11 gnd v4 i/o(b) w19 nc aa12 i/o(d) n4 nc p19 nc t12 nc v5 i/o(b) w20 i/o(e) aa13 i/o(d) n5 i/o(b) p20 i/o(e) t13 i/o(d) v6 nc w21 nc aa14 i/o(d) n6 nc p21 i/o(e) t14 nc v7 i/o(c) w22 i/o(e) aa15 i/o(d) n7 nc p22 i/o(e) t15 i/o(d) v8 i/o(c) y1 i/o(b) aa16 nc n8 vcc r1 i/o(b) t16 gnd v9 nc y2 i/o(b) aa17 nc n9 vcc r2 inref(b) t17 i/o(e) v10 i/o(c) y3 vccpll(2) aa18 i/o(d) n10 gnd r3 i/o(b) t18 i/o(e) v11 nc y4 i/o(c) aa19 i/o(e) n11 gnd r4 i/o(b) t19 nc v12 vded2 y5 i/o(c) aa20 gndpll(1) n12 gnd r5 i/o(b) t20 nc v13 nc y6 i/o(c) aa21 i/o(e) n13 gnd r6 nc t21 ioctrl(e) v14 i/o(d) y7 i/o(c) aa22 i/o(e) n14 vcc r7 i/o(b) t22 i/o(e) v15 i/o(d) y8 ioctrl(c) ab1 i/o(b) n15 vcc r8 gnd u1 ioctrl(b) v16 inref(d) y9 i/o(c) ab2 gndpll(2) n16 i/o(e) r9 vcc u2 i/o(b) v17 i/o(d) y10 i/o(c) ab3 pllrst(2) n17 vccio(e) r10 vcc u3 ioctrl(b) v18 i/o(e) y11 i/o(d) ab4 i/o(b) n18 i/o(e) r11 gnd u4 i/o(b) v19 i/o(e) y12 nc ab5 i/o(b) n19 i/o(e) r12 vded u5 i/o(b) v20 i/o(e) y13 nc ab6 i/o(c) n20 i/o(e) r13 vcc u6 i/o(c) v21 i/o(e) y14 i/o(d) ab7 i/o(c) n21 i/o(e) r14 vcc u7 vccio(c) v22 i/o(e) y15 ioctrl(d) ab8 ioctrl(c) n22 i/o(e) r15 gnd u8 nc w1 i/o(b) y16 i/o(d) ab9 i/o(c) p1 nc r16 i/o(d) u9 vccio(c) w2 i/o(b) y17 i/o(d) ab10 i/o(c) p2 i/o(b) r17 vccio(e) u10 i/o(c) w3 i/o(b) y18 i/o(e) ab11 nc p3 i/o(b) r18 i/o(e) u11 vccio(c) w4 i/o(b) y19 pllout(0) ab12 i/o(d) p4 i/o(b) r19 i/o(e) u12 vccio(d) w5 i/o(b) y20 pllrst(1) ab13 i/o(d) p5 i/o(b) r20 i/o(e) u13 i/o(d) w6 i/o(c) y21 i/o(e) ab14 nc p6 vccio(b) r21 i/o(e) u14 vccio(d) w7 nc y22 i/o(e) ab15 i/o(d) p7 i/o(b) r22 i/o(e) u15 nc w8 nc aa1 tdo ab16 ioctrl(d) p8 vcc t1 i/o(b) u16 vccio(d) w9 nc aa2 pllout(1) ab17 i/o(d) p9 gnd t2 i/o(b) u17 vccio(e) w10 nc aa3 gnd ab18 i/o(d) p10 vcc t3 i/o(b) u18 i/o(e) w11 i/o(c) aa4 i/o(b) ab19 i/o(e) p11 gnd t4 i/o(b) u19 i/o(e) w12 nc aa5 i/o(c) ab20 gnd p12 vcc t5 i/o(b) u20 ioctrl(e) w13 i/o(d) aa6 i/o(c) ab21 vccpll(1) p13 vcc t6 vccio(b) u21 nc w14 nc aa7 nc ab22 i/o(e) p14 gnd t7 gnd u22 inref(e) w15 i/o(d) aa8 inref(c) p15 vded t8 i/o(c) v1 i/o(b) w16 nc aa9 nc table 33: ql6250e - 484 pbga pinout table (continued) ball function ball function ball function ball function ball function ball function ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 53 ql6325e - 208 pqfp pinout diagram eclipse-e ql6325e-6pq208c www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 54 ql6325e - 208 pqfp pinout table table 34: ql6325e - 208 pqfp pinout table pin function pin function pin function pin function pin function 1 pllrst(3) 43 i/o(b) 85 i/o(d) 127 clk(5)/pllin(3) 169 ioctrl(g) 2 vccpll(3) 44 vccio(b) 86 vcc 128 clk(6) 170 inref(g) 3 gnd 45 i/o(b) 87 i/o(d) 129 vded 171 ioctrl(g) 4 gnd 46 vcc 88 i/o(d) 130 clk(7) 172 i/o(g) 5 i/o(a) 47 i/o(b) 89 vcc 131 vcc 173 i/o(g) 6 i/o(a) 48 i/o(b) 90 i/o(d) 132 clk(8) 174 i/o(g) 7 i/o(a) 49 gnd 91 i/o(d) 133 tms 175 vcc 8 vccio(a) 50 tdo 92 ioctrl(d) 134 i/o(f) 176 i/o(g) 9 i/o(a) 51 pllout(1) 93 inref(d) 135 i/o(f) 177 vccio(g) 10 i/o(a) 52 gndpll(2) 94 ioctrl(d) 136 i/o(f) 178 gnd 11 ioctrl(a) 53 gnd 95 i/o(d) 137 gnd 179 i/o(g) 12 vcc 54 vccpll(2) 96 i/o(d) 138 vccio(f) 180 i/o(g) 13 inref(a) 55 pllrst(2) 97 i/o(d) 139 i/o(f) 181 i/o(g) 14 ioctrl(a) 56 vded 98 vccio(d) 140 i/o(f) 182 vcc 15 i/o(a) 57 i/o(c) 99 i/o(d) 141 i/o(f) 183 tck 16 i/o(a) 58 gnd 100 i/o(d) 142 i/o(f) 184 vded2 17 i/o(a) 59 i/o(c) 101 vpump 143 i/o(f) 185 i/o(h) 18 i/o(a) 60 vccio(c) 102 pllout(0) 144 ioctrl(f) 186 i/o(h) 19 vccio(a) 61 i/o(c) 103 gnd 145 inref(f) 187 i/o(h) 20 i/o(a) 62 i/o(c) 104 gndpll(1) 146 vcc 188 gnd 21 gnd 63 i/o(c) 105 pllrst(1) 147 ioctrl(f) 189 vccio(h) 22 i/o(a) 64 i/o(c) 106 vccpll(1) 148 i/o(f) 190 i/o(h) 23 tdi 65 i/o(c) 107 i/o(e) 149 i/o(f) 191 i/o(h) 24 clk(0) 66 i/o(c) 108 gnd 150 vccio(f) 192 ioctrl(h) 25 clk(1) 67 ioctrl(c) 109 i/o(e) 151 i/o(f) 193 i/o(h) 26 vcc 68 inref(c) 110 i/o(e) 152 i/o(f) 194 inref(h) 27 clk(2)/pllin(2) 69 ioctrl(c) 111 vccio(e) 153 gnd 195 vcc 28 clk(3)/pllin(1) 70 i/o(c) 112 i/o(e) 154 i/o(f) 196 ioctrl(h) 29 vded 71 i/o(c) 113 vcc 155 pllout(3) 197 i/o(h) 30 clk(4) dedclk pllin(0) 72 vccio(c) 114 i/o(e) 156 gndpll(0) 198 i/o(h) 31 i/o(b) 73 i/o(c) 115 i/o(e) 157 gnd 199 i/o(h) 32 i/o(b) 74 i/o(c) 116 i/o(e) 158 vccpll(0) 200 i/o(h) 33 gnd 75 gnd 117 ioctrl(e) 159 pllrst(0) 201 i/o(h) 34 vccio(b) 76 vcc 118 inref(e) 160 gnd 202 i/o(h) 35 i/o(b) 77 i/o(c) 119 ioctrl(e) 161 i/o(g) 203 vccio(h) 36 i/o(b) 78 trstb 120 i/o(e) 162 vccio(g) 204 gnd 37 i/o(b) 79 vded2 121 i/o(e) 163 i/o(g) 205 i/o(h) 38 i/o(b) 80 i/o(d) 122 vccio(e) 164 i/o(g) 206 pllout(2) 39 ioctrl(b) 81 i/o(d) 123 gnd 165 vcc 207 gnd 40 inref(b) 82 i/o(d) 124 i/o(e) 166 i/o(g) 208 gndpll(3) 41 ioctrl(b) 83 gnd 125 i/o(e) 167 i/o(g) 42 i/o(b) 84 vccio(d) 126 i/o(e) 168 i/o(g) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 55 ql6325e - 280 lfbga pinout diagram top bottom eclipse-e ql6325e-6pt280c pin a1 corner www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 56 ql6325e - 280 lfbga pinout table table 35: 280 ql6325e - lfbga pinout table ball function ball function ball function ball function ball function ball function a1 pllout(3) c10 clk(5)/ pllin(3) e19 ioctrl(d) k16 i/o(c) r4 i/o(h) u13 i/o(b) a2 gndpll(0) c11 vccio(e) f1 inref(g) k17 i/o(d) r5 gnd u14 ioctrl(b) a3 i/o(f) c12 i/o(e) f2 ioctrl(g) k18 i/o(c) r6 gnd u15 vccio(b) a4 i/o(f) c13 i/o(e) f3 i/o(g) k19 trstb r7 vcc u16 i/o(b) a5 i/o(f) c14 i/o(e) f4 i/o(g) l1 i/o(h) r8 vcc u17 tdo a6 ioctrl(f) c15 vccio(e) f5 gnd l2 i/o(h) r9 gnd u18 pllrst(2) a7 i/o(f) c16 i/o(e) f15 vcc l3 vccio(h) r10 gnd u19 i/o(b) a8 i/o(f) c17 i/o(e) f16 ioctrl(d) l4 i/o(h) r11 vcc v1 pllout(2) a9 i/o(f) c18 i/o(e) f17 i/o(d) l5 vcc r12 vcc v2 gndpll(3) a10 clk(7) c19 i/o(e) f18 i/o(d) l15 gnd r13 vcc v3 gnd a11 i/o(e) d1 i/o(g) f19 i/o(d) l16 i/o(c) r14 vded v4 i/o(a) a12 i/o(e) d2 i/o(g) g1 i/o(g) l17 vccio(c) r15 gnd v5 i/o(a) a13 i/o(e) d3 i/o(f) g2 i/o(g) l18 i/o(c) r16 i/o(c) v6 ioctrl(a) a14 ioctrl(e) d4 i/o(f) g3 ioctrl(g) l19 i/o(c) r17 vccio(c) v7 i/o(a) a15 i/o(e) d5 i/o(f) g4 i/o(g) m1 i/o(h) r18 i/o(c) v8 i/o(a) a16 i/o(e) d6 i/o(f) g5 vcc m2 i/o(h) r19 i/o(c) v9 i/o(a) a17 i/o(e) d7 i/o(f) g15 vcc m3 i/o(h) t1 i/o(h) v10 clk(1) a18 pllrst(1) d8 i/o(f) g16 i/o(d) m4 i/o(h) t2 i/o(h) v11 clk(4)/ dedclk/ pllin(0) a19 gnd d9 clk(8) g17 i/o(d) m5 vcc t3 i/o(a) v12 i/o(b) b1 pllrst(0) d10 i/o(e) g18 i/o(d) m15 vded t4 i/o(a) v13 i/o(b) b2 gnd d11 i/o(e) g19 i/o(d) m16 inref(c) t5 i/o(a) v14 inref(b) b3 i/o(f) d12 i/o(e) h1 i/o(g) m17 i/o(c) t6 ioctrl(a) v15 i/o(b) b4 i/o(f) d13 inref(e) h2 i/o(g) m18 i/o(c) t7 i/o(a) v16 i/o(b) b5 i/o(f) d14 i/o(e) h3 i/o(g) m19 i/o(c) t8 i/o(a) v17 i/o(b) b6 inref(f) d15 i/o(e) h4 i/o(g) n1 ioctrl(h) t9 i/o(a) v18 gndpll(2) b7 i/o(f) d16 i/o(d) h5 vcc n2 i/o(h) t10 i/o(a) v19 gnd b8 i/o(f) d17 i/o(d) h15 vcc n3 i/o(h) t11 clk(3)/ pllin(1) w1 gnd b9 tms d18 i/o(d) h16 vded2 n4 i/o(h) t12 i/o(b) w2 pllrst(3) b10 clk(6) d19 i/o(d) h17 i/o(d) n5 vcc t13 i/o(b) w3 i/o(a) b11 i/o(e) e1 i/o(g) h18 i/o(d) n15 vcc t14 i/o(b) w4 i/o(a) b12 i/o(e) e2 i/o(g) h19 i/o(d) n16 i/o(c) t15 i/o(b) w5 i/o(a) b13 ioctrl(e) e3 vccio(g) j1 i/o(g) n17 i/o(c) t16 i/o(b) w6 i/o(a) b14 i/o(e) e4 i/o(f) j2 i/o(g) n18 ioctrl(c) t17 vccpll(2) w7 i/o(a) b15 i/o(e) e5 gnd j3 vccio(g) n19 ioctrl(c) t18 i/o(b) w8 i/o(a) b16 i/o(e) e6 vcc j4 i/o(g) p1 i/o(h) t19 i/o(b) w9 tdi b17 vccpll(1) e7 vcc j5 gnd p2 i/o(h) u1 i/o(a) w10 clk(2)/ pllin(2) b18 gndpll(1) e8 vded j15 vcc p3 ioctrl(h) u2 i/o(a) w11 i/o(b) b19 pllout(0) e9 vcc j16 i/o(c) p4 inref(h) u3 vccpll(3) w12 i/o(b) c1 i/o(f) e10 gnd j17 vccio(d) p5 vcc u4 i/o(a) w13 i/o(b) c2 vccpll(0) e11 gnd j18 i/o(d) p15 gnd u5 vccio(a) w14 ioctrl(b) c3 i/o(f) e12 vcc j19 i/o(d) p16 i/o(c) u6 inref(a) w15 i/o(b) c4 i/o(f) e13 vcc k1 vded2 p17 i/o(c) u7 i/o(a) w16 i/o(b) c5 vccio(f) e14 gnd k2 tck p18 i/o(c) u8 i/o(a) w17 i/o(b) c6 ioctrl(f) e15 vpump k3 i/o(g) p19 i/o(c) u9 vccio(a) w18 i/o(b) c7 i/o(f) e16 i/o(d) k4 i/o(g) r1 i/o(h) u10 clk(0) w19 pllout(1) c8 i/o(f) e17 vccio(d) k5 gnd r2 i/o(h) u11 vccio(b) c9 vccio(f) e18 inref(d) k15 gnd r3 vccio(h) u12 i/o(b) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 57 ql6325e - 484 pbga pinout diagram top bottom eclipse-e ql6325e-6ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner pin a1 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 58 ql6325e - 484 pbga pinout table table 36: ql6325e - 484 pbga pinout table ball function ball function ball function ball function ball function ball function a1 i/o(a) c1 i/o(a) e1 ioctrl(a) g1 i/o(a) j1 i/o(a) l1 clk(4)/ dedclk/ pllin(0) a2 pllrst(3) c2 i/o(a) e2 i/o(a) g2 i/o(a) j2 i/o(a) l2 clk(0) a3 i/o(a) c3 vccpll(3) e3 i/o(a) g3 i/o(a) j3 i/o(a) l3 clk(2)/pllin(2) a4 i/o(a) c4 pllout(2) e4 i/o(a) g4 i/o(a) j4 i/o(a) l4 i/o(a) a5 i/o(a) c5 i/o(a) e5 i/o(a) g5 i/o(a) j5 i/o(a) l5 i/o(a) a6 i/o(h) c6 i/o(h) e6 i/o(h) g6 i/o(a) j6 i/o(a) l6 i/o(a) a7 i/o(h) c7 i/o(h) e7 nc g7 gnd j7 i/o(a) l7 gnd a8 ioctrl(h) c8 i/o(h) e8 i/o(h) g8 i/o(h) j8 vcc l8 gnd a9 i/o(h) c9 ioctrl(h) e9 i/o(h) g9 i/o(h) j9 gnd l9 gnd a10 nc c10 i/o(h) e10 i/o(h) g10 i/o(h) j10 vcc l10 gnd a11 nc c11 i/o(h) e11 vded2 g11 i/o(g) j11 vcc l11 gnd a12 tck c12 i/o(h) e12 i/o(g) g12 gnd j12 gnd l12 gnd a13 i/o(g) c13 i/o(g) e13 i/o(g) g13 i/o(g) j13 vcc l13 gnd a14 i/o(g) c14 i/o(g) e14 i/o(g) g14 i/o(g) j14 gnd l14 vcc a15 i/o(g) c15 i/o(g) e15 ioctrl(g) g15 i/o(g) j15 vcc l15 vcc a16 i/o(g) c16 i/o(g) e16 i/o(g) g16 vpump j16 i/o(f) l16 clk(6) a17 i/o(g) c17 i/o(g) e17 inref(g) g17 vccio(f) j17 vccio(f) l17 vccio(f) a18 i/o(g) c18 i/o(g) e18 i/o(g) g18 i/o(f) j18 i/o(f) l18 i/o(f) a19 i/o(f) c19 i/o(f) e19 i/o(f) g19 i/o(f) j19 i/o(f) l19 clk(8) a20 gnd c20 gndpll(0) e20 i/o(f) g20 i/o(f) j20 i/o(f) l20 i/o(f) a21 pllout(3) c21 i/o(f) e21 i/o(f) g21 inref(f) j21 i/o(f) l21 i/o(f) a22 i/o(f) c22 i/o(f) e22 i/o(f) g22 i/o(f) j22 i/o(f) l22 i/o(f) b1 i/o(a) d1 i/o(a) f1 i/o(a) h1 i/o(a) k1 tdi m1 i/o(b) b2 gnd d2 i/o(a) f2 inref(a) h2 i/o(a) k2 i/o(a) m2 i/o(b) b3 gndpll(3) d3 i/o(a) f3 i/o(a) h3 i/o(a) k3 i/o(a) m3 i/o(b) b4 gnd d4 i/o(a) f4 i/o(a) h4 i/o(a) k4 i/o(a) m4 clk(3)/pllin(1) b5 i/o(a) d5 i/o(a) f5 i/o(a) h5 ioctrl(a) k5 i/o(a) m5 i/o(b) b6 i/o(h) d6 i/o(h) f6 vccio(a) h6 vccio(a) k6 vccio(a) m6 vccio(b) b7 i/o(h) d7 i/o(h) f7 vccio(h) h7 i/o(h) k7 i/o(a) m7 clk(1) b8 inref(h) d8 i/o(h) f8 i/o(h) h8 gnd k8 vcc m8 vcc b9 i/o(h) d9 i/o(h) f9 vccio(h) h9 vcc k9 vcc m9 vcc b10 i/o(h) d10 i/o(h) f10 i/o(h) h10 vcc k10 gnd m10 gnd b11 i/o(h) d11 i/o(h) f11 vccio(h) h11 vded k11 gnd m11 gnd b12 nc d12 i/o(g) f12 vccio(g) h12 gnd k12 gnd m12 gnd b13 nc d13 i/o(g) f13 i/o(g) h13 vcc k13 gnd m13 gnd b14 nc d14 i/o(g) f14 vccio(g) h14 vcc k14 vcc m14 gnd b15 i/o(g) d15 ioctrl(g) f15 nc h15 gnd k15 vcc m15 gnd b16 i/o(g) d16 i/o(g) f16 vccio(g) h16 i/o(f) k16 i/o(f) m16 gnd b17 i/o(g) d17 i/o(g) f17 nc h17 i/o(f) k17 i/o(f) m17 i/o(e) b18 i/o(g) d18 i/o(f) f18 i/o(f) h18 i/o(f) k18 i/o(f) m18 i/o(e) b19 pllrst(0) d19 vccpll(0) f19 i/o(f) h19 i/o(f) k19 i/o(f) m19 i/o(e) b20 i/o(f) d20 i/o(f) f20 ioctrl(f) h20 i/o(f) k20 i/o(f) m20 clk(7) b21 i/o(f) d21 i/o(f) f21 i/o(f) h21 i/o(f) k21 i/o(f) m21 clk(5)/pllin(3) b22 i/o(f) d22 i/o(f) f22 ioctrl(f) h22 i/o(f) k22 i/o(f) m22 tms ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 59 n1 i/o(b) p16 i/o(e) t9 nc v2 i/o(b) w17 i/o(d) aa10 i/o(c) n2 i/o(b) p17 i/o(e) t10 trstb v3 i/o(b) w18 i/o(e) aa11 i/o(c) n3 i/o(b) p18 i/o(e) t11 gnd v4 i/o(b) w19 i/o(e) aa12 i/o(d) n4 i/o(b) p19 i/o(e) t12 nc v5 i/o(b) w20 i/o(e) aa13 i/o(d) n5 i/o(b) p20 i/o(e) t13 i/o(d) v6 i/o(c) w21 i/o(e) aa14 i/o(d) n6 i/o(b) p21 i/o(e) t14 nc v7 i/o(c) w22 i/o(e) aa15 i/o(d) n7 i/o(b) p22 i/o(e) t15 i/o(d) v8 i/o(c) y1 i/o(b) aa16 i/o(d) n8 vcc r1 i/o(b) t16 gnd v9 nc y2 i/o(b) aa17 i/o(d) n9 vcc r2 inref(b) t17 i/o(e) v10 i/o(c) y3 vccpll(2) aa18 i/o(d) n10 gnd r3 i/o(b) t18 i/o(e) v11 i/o(c) y4 i/o(c) aa19 i/o(e) n11 gnd r4 i/o(b) t19 i/o(e) v12 vded2 y5 i/o(c) aa20 gndpll(1) n12 gnd r5 i/o(b) t20 i/o(e) v13 nc y6 i/o(c) aa21 i/o(e) n13 gnd r6 i/o(b) t21 ioctrl(e) v14 i/o(d) y7 i/o(c) aa22 i/o(e) n14 vcc r7 i/o(b) t22 i/o(e) v15 i/o(d) y8 ioctrl(c) ab1 i/o(b) n15 vcc r8 gnd u1 ioctrl(b) v16 inref(d) y9 i/o(c) ab2 gndpll(2) n16 i/o(e) r9 vcc u2 i/o(b) v17 i/o(d) y10 i/o(c) ab3 pllrst(2) n17 vccio(e) r10 vcc u3 ioctrl(b) v18 i/o(e) y11 i/o(d) ab4 i/o(b) n18 i/o(e) r11 gnd u4 i/o(b) v19 i/o(e) y12 i/o(d) ab5 i/o(b) n19 i/o(e) r12 vded u5 i/o(b) v20 i/o(e) y13 i/o(d) ab6 i/o(c) n20 i/o(e) r13 vcc u6 i/o(c) v21 i/o(e) y14 i/o(d) ab7 i/o(c) n21 i/o(e) r14 vcc u7 vccio(c) v22 i/o(e) y15 ioctrl(d) ab8 ioctrl(c) n22 i/o(e) r15 gnd u8 nc w1 i/o(b) y16 i/o(d) ab9 i/o(c) p1 i/o(b) r16 i/o(d) u9 vccio(c) w2 i/o(b) y17 i/o(d) ab10 i/o(c) p2 i/o(b) r17 vccio(e) u10 i/o(c) w3 i/o(b) y18 i/o(e) ab11 i/o(c) p3 i/o(b) r18 i/o(e) u11 vccio(c) w4 i/o(b) y19 pllout(0) ab12 i/o(d) p4 i/o(b) r19 i/o(e) u12 vccio(d) w5 i/o(b) y20 pllrst(1) ab13 i/o(d) p5 i/o(b) r20 i/o(e) u13 i/o(d) w6 i/o(c) y21 i/o(e) ab14 i/o(d) p6 vccio(b) r21 i/o(e) u14 vccio(d) w7 nc y22 i/o(e) ab15 i/o(d) p7 i/o(b) r22 i/o(e) u15 nc w8 i/o(c) aa1 tdo ab16 ioctrl(d) p8 vcc t1 i/o(b) u16 vccio(d) w9 i/o(c) aa2 pllout(1) ab17 i/o(d) p9 gnd t2 i/o(b) u17 vccio(e) w10 i/o(c) aa3 gnd ab18 i/o(d) p10 vcc t3 i/o(b) u18 i/o(e) w11 i/o(c) aa4 i/o(b) ab19 i/o(e) p11 gnd t4 i/o(b) u19 i/o(e) w12 i/o(d) aa5 i/o(c) ab20 gnd p12 vcc t5 i/o(b) u20 ioctrl(e) w13 i/o(d) aa6 i/o(c) ab21 vccpll(1) p13 vcc t6 vccio(b) u21 i/o(e) w14 i/o(d) aa7 i/o(c) ab22 i/o(e) p14 gnd t7 gnd u22 inref(e) w15 i/o(d) aa8 inref(c) p15 vded t8 i/o(c) v1 i/o(b) w16 nc aa9 i/o(c) table 36: ql6325e - 484 pbga pinout table (continued) ball function ball function ball function ball function ball function ball function www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 60 package mechanical drawings 208 pqfp packaging drawing ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 61 280 lfbga packaging drawing www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 62 484 pbga packaging drawing ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipse-e family data sheet rev. a 63 packaging information the eclipse-e product family packaging in formation is presented in table 37 . note: military temperature range plastic packages will be added as follow on products to the commercial and industrial products. ordering information table 37: packaging options device information ql6250/ql6325e pin/ball pitch package definitions a a. pqfp = plastic quad flat pack bga = ball grid array lfbga = low profile fine pitch ball grid array 208 pqfp 0.50 mm 280 lfbga 0.80 mm 484 bga 1.0 mm ql 6 3 25e - 6 pq20 8 c q u icklogic device eclip s e-e device p a rt n u m b er 6250e 6 3 25e s peed gr a de oper a ting r a nge c = commerci a l i = ind us tri a l m = milit a ry p a ck a ge code pq20 8 (pqn20 8 )* = 20 8 -pin pqfp (0.5 mm) pt2 8 0 (ptn2 8 0)* = 2 8 0-pin lfbga (0. 8 mm) p s 4 8 4 (p s n4 8 4)*= 4 8 4-pin bga (1.0 mm) 6 = f as t 7 = f as ter 8 = f as te s t * le a d-free p a ck a ging i s a v a il ab le, cont a ct q u icklogic reg a rding a v a il ab ility ( s ee cont a ct inform a tion). www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipse-e family data sheet rev. a 64 contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe ? except german y/benelux) +(49) 89 930 86 170 (germany/benelux) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com revision history copyright and trademark information copyright ? 2006 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited. quicklogic and the quicklogic logo, vialink, and quickworks are registered trademarks of quickl ogic corporation; eclipse and spde are trademarks of quicklogic corporation. revision date comments a february 2006 mehul kochar and kathleen murchek combined ql6250e and ql6325 data sheets into one eclipse-e family data sheet. added lead-free packaging to ordering information. |
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